Creating and Implementing a Sobel Filter IP core on the PYNQ Z2 FPGA platform
This blog post explores the development and implementation of Sobel filter IP core on the PYNQ Z2 FPGA. You will learn to design the filter in Vitis HLS, how to export and integrate the sole IP core in Vivado and finally control the Sobel (using DMA) in PYNQ Jupyter Notebook.