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Protostar Labs Acquires Photon Logic
Protostar Labs has entered into an agreement to acquire Photon Logic, strengthening our advanced vision and onboard data processing capabilities for space applications.
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News
Vegvisir and Protostar Labs Sign Memorandum of Understanding
Vegvisir has signed a Memorandum of Understanding (MoU) with Protostar Labs, establishing a framework for strategic collaboration at the intersection of artificial intelligence and mixed reality situational awareness. The agreement focuses on exploring advanced capabilities that enhance decision-making, operational safety, and user effectiveness in complex environments.
Space
Mitigating radiation effects in FPGAs
The TMR VHDL Library makes it easy to add Triple Modular Redundancy to your FPGA designs. By triplicating critical logic and using a voter circuit, it protects against faults from Single Event Effects. With a simple USE_TMR switch, you can turn redundancy on or off, speeding up development while ensuring your IP can be industrial- or space-grade ready.
Space
Protostar Labs signs ESA contract for chromosphere monitoring instrument
Protostar Labs is happy to announce the signing of a new contract with the European Space Agency for the development of CROMIS, the ChROmosphere Monitoring InStrument. Funded under ESA's Call for Proposals for Croatian entities, this project, beginning on September 15, 2025, marks a major milestone for Croatia in space science and astrophysics.
News
Exhibition at DEFCROS Public Safety & Defense Expo
A showcase of our latest technologies at the first international DEFCROS Public & Safety Expo in Osijek.
Space
Attendance of the International Astronautical Congress 20204 in Milan
Sharing our experiences at the IAC 2024 Milan
News
Protostar Labs is attending IAC2024 in Milan
We are thrilled to share that Protostar Labs will attend the 75th International Astronautical Congress (IAC 2024). The congress will be held in Milan, Italy from the 14th to the 18th of October, 2024.
FPGA
Exploring VDMA and Implementing Loop Testing on the PYNQ Z2 FPGA Platform
In our previous blog post, we explored the development and implementation of a Sobel filter IP core on the PYNQ Z2 FPGA. There we explained how to design the filter in Vitis HLS, export and integrate the IP (Intellectual Property) core into Vivado, and finally control the Sobel Filter using Direct Access Memory (DMA) in the PYNQ environment. In this post, we will be using a different approach called Video Direct Memory Access (VDMA). It is similar to the DMA, but designed for video applications.
FPGA
Creating and Implementing a Sobel Filter IP core on the PYNQ Z2 FPGA platform
This blog post explores the development and implementation of Sobel filter IP core on the PYNQ Z2 FPGA. You will learn to design the filter in Vitis HLS, how to export and integrate the sole IP core in Vivado and finally control the Sobel (using DMA) in PYNQ Jupyter Notebook.
Space
Protostar Labs successfully deploys software on OPS-SAT satellite in space!
We’re so happy to announce that we have successfully deployed our code on the OPS-SAT satellite in space!